1. Field of the Invention
The present invention relates to an active matrix substrate which is for use in a liquid crystal television set, a liquid crystal monitor device, a laptop computer, or the like. The present invention also relates to a display device including the active matrix substrate.
2. Description of the Related Art
Liquid crystal display devices are utilized in various fields because of their thinness and low power consumption. In particular, liquid crystal display devices of an active matrix type, comprising a switching element such as a thin film transistor (referred to as a “TFT”) for each pixel, have a high contrast ratio and excellent response characteristics, and are used in television sets, monitor devices, and laptop computers because of their high performance. The market scale thereof has been increasing in the recent years.
On an active matrix substrate which is used in an active matrix type liquid crystal display device, a plurality of scanning lines and a plurality of signal lines which intersect these scanning lines via an insulating film are formed, and thin film transistors for switching the pixels are provided near the intersections between the scanning lines and the signal lines.
A capacitance which is formed at each intersection between a scanning line and a signal line (referred to as a “parasitic capacitance”) may cause deterioration in the display quality. Therefore, it is preferable that the capacitance values of the parasitic capacitances are small.
Accordingly, Japanese Laid-Open Patent Publication No. 5-61069 (Patent Document 1) discloses a technique in which the scanning lines and signal lines are made narrower in width at such intersections than at any other portion, thus reducing the area of each intersection and reducing the parasitic capacitance which is formed at each intersection.
However, narrowing the width of the wiring lines, even if locally, will increase the resistance values of the wiring lines, thus causing signal blunting. Moreover, since narrowing the width of the wiring lines will lead to an increased probability of line breaking, it is generally necessary to secure about 50% of the original width. Therefore, the aforementioned technique of Patent Document 1 has its limit in reducing the parasitic capacitance of the intersections. In recent years, liquid crystal display devices have increased in size and resolution. In a large-sized and high-resolution liquid crystal display device, broader wiring line widths are used in order to reduce wiring resistance, and there is an increased number of intersections between wiring lines, which results in an increased parasitic capacitance formed at each intersection. This makes the aforementioned signal blunting more outstanding.
Another technique for reducing the capacitance which is generated at each intersection between a scanning line and a signal line might be to increase the thickness of the insulating film which covers the scanning lines. However, when an insulating film which covers the scanning lines partially functions as a gate insulating film, as in the case of bottom-gate type TFTs or the like, the driving ability of the TFTs will be degraded by increasing the thick of this insulating film.